1. Field of the Invention
The present invention relates generally to semiconductor devices that respond to test mode signals. In particular, the invention relates to a semiconductor device that produces a glitch noise in response to an externally supplied test signal.
2. Description of the Related Art
One common diagnostic routine used to test the performance of large scale integrated circuits (LSI's) such as semiconductor memory devices, is the so-called glitch "noise" test. This routine makes it possible for LSI manufactures to gauge how a particular device responds to a low frequency interference on glitch noise. During this test, glitch noise is typically input to the LSI during its operation to gauge LSI function in the presence of unwanted interference. The recent increases in LSI operational speeds, however, require increasing shorter glitch noise signals. Consequently, LSI manufacturers are concerned with developing reliable LSI glitch test routines with increasingly shorter glitch noise input.
Noise tests for semiconductor memory devices are conventionally carried out by supplying an address signal containing glitch noise to the semiconductor memory device from a semiconductor testing apparatus, i.e., a tester. Based on a noise testing program, the tester generates an address signal containing glitch noise. To accommodate noise in an address signal, the noise testing program designs an address signal AD0, for example, to have a period t.sub.w for signal level changes as shown in FIG. 1A. When the time period t.sub.w is shortened to time period t.sub.w 0 as shown in FIG. 1B, a glitch noise GN may be incorporated into the address signal AD0 and output from the tester.
An address decoder circuit in the semiconductor memory receives the address signal AD0 containing the glitch noise and decodes a select signal from the address signal. Based on the select signal, a single memory cell is selected to store either "0" or "1" depending on the testing pattern. When the tester supplies the semiconductor memory device with an address signal having no glitch noise, cell data is read from a memory cell selected based on the address signal. The tester then identifies whether the data read from the cell coincides with data written therein.
Should the programmed time period t.sub.w be too short in duration, however, conventional testers generally cannot generate address signals with glitch noise waveforms like that shown in FIG. 1B. Conventional noise testing is thus limited to testing routines utilizing address signals with sufficiently long t.sub.w period characteristics. In particular, t.sub.w period characteristics must be set longer than that of the noise generated by the tester. This requirement limits the types of testers which can be used for glitch noise testing. In fact, many types of testers are unable to perform glitch noise testing.
A further disadvantage of conventional glitch noise testing is the labor and time it takes to program and operate the tester. Glitch noise testing, consequently, requires a considerable investment in human and financial resources.